1. Field of the Invention
The present invention relates to a non-volatile memory device. In particular, the present invention relates to single-poly, one-transistor (1-T) one-time programmable (OTP) memory and a method to program and read such OTP memory.
2. Description of the Prior Art
Currently, non-volatile memory is one of the most popular electronic storage media for saving information. One of the most important features of all is that the information stored in the non-volatile memory will not disappear once the power supply is cut off. Generically speaking, memory devices such as hard drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory are non-volatile memory devices, because all information is still available in the absence of power supply.
According to the programming times limit, non-volatile memory devices are divided into multi-time programmable memory (MTP) and one-time programmable memory (OTP).
MTP is multi-readable and multi-writable. For example, EEPROM and flash memory are designedly equipped with some corresponding electric circuits to support different operations such as programming, erasing and reading. Because OTP is one-time programmable only, it functions perfectly with electric circuits with mere programming and reading functions. Electric circuits for erasing operation are not required. Therefore, the electric circuits for OTP are much simpler than those for the MTP to minimize the production procedures and cost.
To enhance the applicability of OTP, the information stored in the OTP can be erased by the methods similar to those (such as UV light radiation) of EPROM. It is also suggested that OTP can be controlled to provide several times of reading and programming operations by simple circuit design.
Multi-time programmable memory units and one-time programmable memory units share similar stacking structures. Structurally speaking, they are divided into double-poly non-volatile memory and single-poly non-volatile memory. In the double-poly non-volatile memory, it usually comprises a floating gate for the storage of charges, an insulation layer (an ONO composite layer of silicon oxide/silicon nitride/silicon oxide for example), and a control gate for controlling the access of data. The operation of the memory unit is based on the principle of electric capacity, i.e. induced charges are stored in the floating gate to change the threshold voltage of the memory unit for determining the data status of “0” and “1”.
On the other hand, in the advanced logic process, the embedding of double-poly non-volatile memory will greatly increase the cost and changes the electrical characteristics of devices because of additional thermal budget, followed by re-adjusting the characteristics of the devices back to origin device targets, so the schedule will be inevitably delayed. Consequently, single-poly non-volatile memory is advantageous and would be regarded as the embedded non-volatile memory of good competitiveness of the next generation.
Because the single-poly non-volatile memory is compatible with regular CMOS process, it is usually applied in the field of embedded memory, embedded non-volatile memory in the mixed-mode circuits and micro-controllers for example.
Please refer to U.S. Pat. No. 5,761,126 “SINGLE POLY EPROM CELL THAT UTILIZES A REDUCED PROGRAMMING VOLTAGE TO PROGRAM THE CELL”, U.S. Pat. No. 6,930,002 “METHOD FOR PROGRAMMING SINGLE-POLY EPROM AT LOW OPERATION VOLTAGES”, and U.S. Pat. No. 6,025,625 “SINGLE-POLY EEPROM CELL STRUCTURE OPERATIONS AND ARRAY ARCHITECTURE” for prior art regarding single-poly non-volatile memory.
The conventional single-poly non-volatile memory still has several disadvantages that need improvement. First, the conventional single-poly non-volatile memory occupies more chip area. So far, no solution is proposed for further miniaturizing the size of the single-poly one-time programmable memory with respect to the semiconductor logic process of 90 nm scale or beyond.
During the miniaturization of the logic process, all operational voltages and the thickness of the gate oxide shrink as well. In the 90 nm technology, for example, the thickest gate oxide layer is about 50 to 60 Å. It is a great challenge for the use of floating gate technique to produce multi-time programmable single-poly non-volatile memory for the reason that the insufficient tunnel oxide thickness deteriorates long term charge retention. On the other hand, it is not compatible with the current logic process to increase the thickness of the oxide layer.
Moreover, it requires higher voltage, at least 8 to 10 volts of couple well voltage for example, for the conventional single-poly non-volatile memory to generate enough electric field across the tunnel oxide layer for programming. Because the required operational voltage is much higher than the VCC voltage (for example supply voltage for input/output circuits VCC=3.3V) supplied, it results in the serious problem of reliability for the gate oxide layers of tens of A in the more advanced nano-process. In addition, it also requires additional high voltage elements and corresponding electric circuits to generate the desired higher voltage.
U.S. Pat. No. 6,822,888 to Peng discloses a semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The semiconductor memory cell is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 angstroms thickness or less, as commonly available from presently available advanced CMOS logic processes. Other references include “A Novel Embedded OTP NVM using Standard Foundry CMOS Logic Technology”, Bernard Aronson, Kilopass, USA, pages 24-26, IEEE Non-Volatile Semiconductor Memory Workshop, 2006.
However, it requires one and half transistors (1.5-T), more specifically, one transistor and one capacitor, to constitute the semiconductor memory cell according to U.S. Pat. No. 6,822,888. Therefore, such memory cell occupies more chip area and the operation is more complicated.